Three image buffer system for card reader



March 13, 1962 l.. G. ALLEN 3,024,598l THREE IMAGE BUFFER SYSTEM FoECARD READER Filed Dec. 15, 195e 2 sheets-sheet 1 COMPARE AML/F/ER &c/ARAcrE/f? REG/STER /7 o/s/r V *l k3 1 5 1 (25 .FM/rm? H ,VW l i (j) C)I l f3 HALF @59er F0@ @40 oz/r/ o 7 \f6 6"/ [Z6 ,P9 gyn k :T: 33 my, hY() 50 coa/vm? g ,QE/v70. R 0 cw? R *Z3 P34 PULSE x T f INVENTOR 32 LaweGAleza 80 00m/rfi? l BY 24 Ww/.4 Ma

ATTORNEYS L. G. ALLEN March 13, 1962 THREE IMAGE BUFFER SYSTEM FOR CARDREADER l5, 1958 2 Sheets-Sheet 2 Filed Dec United States Patent 'C M'3,024,931 THREE IMAGE BUFFER SYSTEM FR CARD READER Lowell G. Allen,Hopewell Junction, NX., assigner to International Business MachinesCorporation, New York, N.Y., a corporation of New York Filed Dec. 15,1955, Ser. No. 780,555 7 Claims. (Cl. 23S-61.7)

This invention relates to a record reading system and more particularlyto a system designed to compare information read from a record card at arst read station with information read therefrom at a second readstation and to compare the read-outs from these two stations and toindicate the lack of comparisons between the two readouts.

It is often necessary to provide checking means to check read-outinformation or data from a record means such as a punched card and thelike and to permit said data to enter the further routines of the systemonly if the check is valid. In a specific embodiment of this invention,an IBM record card having twelve rows and eighty columns of significantareas upon which data can be recorded in the `form of punched holes isread out at a rst read station and at a second read station. Means areprovided to store row-by-row in a iirst storage means such as la corematrix the information read out at the first read station. Means arealso provided for similarly storing the data read out at the second readstation in a second core matrix. With the information from the card nowstored in the lirst and second core matrices, both of said matrices areread out column-by-column and a comparison is made bit-by-bit. Anydifference between two ycorresponding bits constitutes an error. Thispermits isolation of errors to column and rows of storage. `It permitsearly detection of errors and makes error corection easier. Iteliminates the possibility of missing errors due to dropping out orpicking up an even number of bits in the same row as might be the oasein the horizontal redundancy check method,

Particularly this invention provides a system in which data isrepresented by indicia on a first record. Data on a rst record is readout at a first read station into a kfirst storage means such as a corematrix. Data on a second record is next read out at the rst read stationinto a second storage means such as another core matrix. At this timethe first record has been moved to a second read station where it isread out and stored in a third storage means such as a core matrix. Itcan be seen at this part of the cycle that the rst record is stored inthe rst and third core matrices and the second record is stored in thesecond core matrix. 'Ihe first and third core matrices are read out incolumn-by-colurnn fashion to a comparison unit where the data bits arecompared bit by bit and an error signal is provided whenever a lack ofcomparison between associated bits occur.

Next the second record is read out at the second read station and storedin the third core matrix and a third record is read out and stored inthe rst core matrix. Now the second and third core matrices are read outfor comparison. The cycles as above are then repeated for succeedingcards. The capacity for this system is about 1,000 cards per minute.

In the drawings:

FIGURE l is a view show-ing a diagrammatic representation of the cardreader and comparison system constructed in accordance with thisinvention.

FIGURE 2 is a timing chart showing the time relationships during -eachsucceeding cycle of the various inhibit, read in, etc. phases.

Referring rst to FIGURE 1, the numeral 10 identities a drum upon which acard is positioned for reading pur- 3,024,981 Patented Mar. 13, 1962poses. For the purpose of illustration, let it be assumed that therecord is a standard IBM card having twelve columns and eighty rows. Thereading from the read station is accomplished in a row-by-row fashion.There are a plurality of brushes 11, eighty in number, which read thepunched card and provide read-in to the three matrices 12, 15 and 16.The three matrices are comprised of a l2 x 8O array of two state coreseach having a set and a reset state. Normally all of the cores are in areset condition. To set a core requires the application to the core of aread-in current pulse of W amplitude. The read-in from the brushesapplies W/ 2 current to the cores. A digit emitter (not shown) appliesW/2 pulse to line 13 when the lirst column of the card is being read andto line 14 when the second column of the card is being read, etc.synchronized with the read-in from brushes 11. It can be seen that .thedigit emitter for matrix 12 `also supplies the W/Z pulse for matrix 15.The digit emitter for matrix 16 applies the W/2 pulses on lines 17, 18,etc. Switch 19 is normally in the position as shown in this gure with`the switch contact in the lower position. To this switch is applied aninhibit pulse or a reset pulse of R/ 2 amplitude where R is the ampli--tude of current necessary to reset a core. The inhibit pulse is ofsufficient amplitude to prevent the change of state of any core to whichit is applied. It can be seen that the inhibit or R/ 2 pulse may beapplied selectively to the cores in matrix 12 or 15 depending upon theposition of switch 19. From a suitable source (not shown), an R/ 2 pulseis applied on line 20 to all of the cores in matrix 16.

At the second reading station is a similar setup. It includes a drum 21upon which a card is positioned for reading and a plurality of readingbrushes 22.

With data bits stored in the matrices 12, 15 and 16, read-out isobtained by the application of an R/2 pulse on line Ztl to matrix 15 andthrough switch 19 to either matrix 12 or matrix 15 in conjunction withan R/ 2 pulse supplied by the Sil-current drivers 23. The drivers are ofa conventional type and supply R/ 2 pulses sequentially to each of theeighty columns in the three matrices. The particular column supplied isdetermined by the ring counter 24 which may be of a conventional triggertype.

When any two selected matrices are read out for comparison purposes, thebits are fed to the amplifier and character registers 25 and 26. Uponthe coincidence of two R/ 2 current pulses in a set core, the core isreset and the switching thereof is sensed on the sense windingassociated with the core which in this particular case is the samewinding to which the digit emitter pulse is applied. These provideread-out pulses from the switched cores which pulses are fed to theregisters 25 and 26 in bit-bybit fashion as the columns are sequentiallyread out. The registers 25 and 26 function to register the bits suppliedthereto `from the matrices and feed the bits in bit-by-bit fashion tothe comparator 277. There, bit-by-bit comparison is made of associatedbits and the output from the comparitor 27 indicates any lack ofcomparison. The units 25, 25 and 27 may be of any conventional variety.

The thyratron 28 through the condenser 29 applies a W pulse to all ofthe cores in a one-by-eighty matrix identitied -by numeral 30 to set allof these cores. When the ring counter 24 has run out to read out thedata stored in the selected matrices, the eighty counter 31 should havecounted eighty counts. Each time one of the eighty current driverssupplies an R/ 2 pulse to one of the columns in the matrices, an R/ 2pulse is also applied on line 32 to all of the cores in theone-by-eighty matrix 30. So it can be seen Ithat -for a proper operationof the driver 23 each time a driver supplies an R/2 pulse toa column ofcores in the selected matrices this R/2 pulse in cooperation with theR/2 pulse on line 32 to the one-by-eighty matrix should switch thatparticular core and add a count in the counter 31. If at the end of acycle there are less than eighty counts, the output of counter 31 willso indicate by a signal at its output on line 33. The counter isinterrogated by a signal applied to it on line 34.

Let it now be assumed that card 1 is in the first read station. Duringthe first read cycle, matrix will be inhibited by the application of aninhibit pulse through switch 19 with the switch 19 in its down positionas shown. The read brushes 11 read the first row of card 1 intomatrix 1. At this time, the digit emitter applies a W/ 2 pulse to line13. As a result, the first crow of card 1 is read out and stored in thefirst row of matrix 12. The drum then moves the card so that the secondrow is read out and stored in the second row of matrix 12, the digitemitter now supplying a W/ 2 pulse to line 14. The twelve rrows of card1 are by this process stored in matrix 12. All of this time, matrix 15is inhibited. During the second read cycle, card 1 is moved to thesecond read station and positioned on the drum 21. Simultaneously, card2 is moved into reading position in the first read station. The firstcard is by a similar process read into matrix 16. The switch i19 movesto its upper position and matrix 12 is inhibited. Card 2 is read andstored in matrix 15. At this time, card 1 is stored in matrices 12 and16 and card 2 in matrix 15. Then, read-out of matrices 12 and 16 occurs.With switch 19 in the upper position, an R/Z pulse is applied to all ofthe cores in matrix 12. The counter 24 commences its cyclic operationand causes the first current driver in unit 23 to apply an R/Z pulse torow 1 of matrices 12 and 16. An R/Z pulse is applied through switch 19to all of the cores in matrix 12 and on line to all of the cores in core16. As a result., the cores in column 1 of matrix 12 and the cores ofcolumn 1 in matrix 16 are read out to the registers 25 and 26,respectively. It can be seen then that read-out from the selectedmatrices is accomplished column by column to provide parallel read-outon each of the sense lines associated with the respective columns andthereby providing parallel input to the registers 25 and 26. There thebits are stored column-by-column in the register and readoutcolumn-by-column from each of the registers to the comparator 27 forindividual bit-by-bit comparison.

After read-out of matrices 12 and 16, card 2 is still stored in matrix15. Card 3 is now positioned in the first read station and is read outtherefrom and stored in matrix 12. The second card which is now at thesecond tread station is read out therefrom and stored in matrix 16.Matrix 15 is inhibited at this time. Then matrices 15 and .16 are readout to the registers 25 and 26 and from there are compared in thecomparator 27 bit by bit.

In the next cycle of operation, matrix 12 is inhibited and card 3 isread into matrix 16 and card 4 into matrix 15. Next matrix 12 is readout simultaneously with matrix 16 to provide a bit-by-bit comparison incomparator 27.

Referring to FIGURE 2, the four cycles of operation above described areshown and the time sequence of operation is evident from this chart. Thenumbers 12, 15 and 16 refer to the respective matrices of FIGURE 1.

By providing means to connect the brushes in the read stations to thematrices through a plug board, allowance thereby is made if desired forcomplete rearrangement of the data in the record cards.

What has been described is one embodiment of the present invention.Other embodiments obvious to those skilled in the art are contemplatedto be Within the spirit and scope of the accompanying claims.

What is claimed is:

l. A device for comparing record data comprising rst, second and thirdrecord storage means, first and second record sensing means, means firstto store first data sensed by said first record sensing means in saidfirst record storage means, means to second store first data sensed bysaid second record sensing means in said third record storage means,means simultaneously with said last-mentioned 'cans to store second datasensed by said first record sensing means in said second record storagemeans, and means to compare the stored data in said first and thirdrecord storage means.

2. A device for comparing record data comprising first, second and thirdrecord storage means, first and second record sensing means, means tostore during a first time cycle data sensed by said firs-t recordsensing means in one of said first and second record storage means,means to store `during a second time cycle data sensed by said secondrecord sensing means in said third record storage means, means to storeduring said second time cycle data sensed by said first record sensingmeans in said other of said first and second record storage means, andmeans to compare the data stored in said third record storage means andthe data stored in said one record storage means.

3. A device for comparing record data comprising first, second and thirdrecord storage means, first and second record sensing means, means tostore during a first time cycle data sensed by said first record sensingmeans in one of said first and second record storage means, means tostore during a second time cycle data sensed by said second recordsensing means in said third record storage means, means to store duringsaid second time cycle data sensed by said first record sensing means insaid other of said first and second record storage means, means to readout stored data from said third record storage means and from said onerecord storage means, means to compare said read-out data, meanssubsequent to said read-out to store data sensed by said first recordsensing means in said one `of said first and second record storagemeans, means simultaneously with said last-mentioned means to store datasensed by said second record sensing means in said third record storagemeans and means to compare the stored data in said other and said thirdrecord storage means.

4. A device for comparing data represented by indicia on a recordcomprising first, second and third matrices, each comprising a pluralityof storage elements capable of assuming alternate stable states, eachmatrix including at least one element for each unit of indica, rst andsecond sensing means for successively reading said records, read-inwinding means associated with each storage element in said first andsecond matrices coupled to said first sensing means and adapted to beenergized thereby, each element assuming one of said stable states inaccordance with said indicia, inhibit means alternately operable betweensaid first and second matrices, read-in Winding means associated witheach storage element in said third matrix coupled to said second sensingmeans and adapted to be energized thereby, each element assuming one ofsaid stable states in accordance with said indicia, comparing means,first read-out means associated with said third matrix and coupled tosaid comparing device for entry of said records therein, and secondread-out means associated with said first and second matrices andcoupled to said comparing device adapted to enter like records thereincorresponding to the record entered from said third matrix.

5. A device as claimed by claim 4 wherein said storage elements aretwo-state magnetic cores.

6. A device as claimed by claim 5 wherein said inhibit means comprisesinhibit winding means associated with each of said cores in said firstand second matrices and means to alternately apply an inhibiting signalto said first and second matrices.

7. A device as claimed in claim 6 wherein said first readout meanscomprises first read-out Winding means comprises said inhibit windingmeans, means to alternately apply a half reset signal to said rst andsecond matrices cores, said second readout winding means and said meansto apply said coincident half reset signal.

No references cited.

